Examples

Here we have examples on how v2x converts a Verilog module to its corresponding model.xml and pb_type.xml files. These examples are taken from the v2x test cases.

• Clock multiplexing primitive
• Clock
  • Autodetection of clock from flipflop
    • D-Flipflop with one clock
    • D-Flipflop with combinational logic
    • D-Flipflop with two clocks
  • Manually set inputs as clock
    • Manually set input as clock by setting the CLOCK attribute
    • Force input as regular input by setting the CLOCK attribute
    • Set input as clock by name (clk)
    • Set input as clock by name (regex)
  • Manually set outputs as clock
    • Manually set output as clock by setting the CLOCK attribute
    • Set output as clock by name (clk)
  • Multiple clocks
    • Set inputs as clock by name (multiple clock inputs)
    • Set outputs as clock by name (multiple clock outputs)
• DSP examples
  • Combinational DSP
    • Detection of combinational connections
    • Blackbox detection
  • DSP-style block with all inputs registered
    • Detection of combinational connections
    • Blackbox detection
  • DSP-style block with outputs registered
    • Detection of combinational connections
    • Blackbox detection
  • DSP-style block with inputs and outputs registered (single clock)
    • Detection of combinational connections
    • Blackbox detection
  • DSP-style block with inputs and outputs registered using separate clocks
    • Detection of combinational connections
    • Blackbox detection
  • DSP-style block with only one input registered
    • Detection of combinational connections
    • Blackbox detection
  • DSP-style block with different modes
    • Blackbox detection
    • Modes generation
• Basic logic gates
  • NOT gate
  • AND gate
  • NOR gate
  • XOR gate
• Forced non-sequential relations to an input
• Pack pattern annotation
• Verilog to Routing
  • Primitive Block Timing Modeling Tutorial
    • Classical D-Flip-Flop test
      • Clock associations inference
      • Blackbox detection
      • Timings
    • Full Adder Example
      • Detection of combinational connections
      • Blackbox detection
      • Timings
    • LUT with FlipFlop Example
      • Blackbox detection
      • Carry chain inference