Full Adder Example

An example of the classical combinational “full adder” circuit shown in Figure 60 - Full Adder of the “Combinational block” section in the Primitive Block Timing Modeling Tutorial of the Verilog to Routing documentation and reproduced below.

Figure 59 from Verilog to Routing Documentation

Fig. 59 - Full Adder


/home/docs/checkouts/readthedocs.org/user_builds/f4pga-v2x/checkouts/latest/docs/examples/vtr/full-adder/adder.sim.v

adder.sim.v
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(* whitebox *)
module ADDER (
  a, b, cin,
  sum, cout
);
  input wire a;
  input wire b;
  (* carry = "ADDER" *)
  input wire cin;

  (* DELAY_CONST_a   = "300e-12" *)
  (* DELAY_CONST_b   = "300e-12" *)
  (* DELAY_CONST_cin = "300e-12" *)
  output wire sum;

  (* carry = "ADDER" *)
  (* DELAY_CONST_a   = "300e-12" *)
  (* DELAY_CONST_b   = "300e-12" *)
  (* DELAY_CONST_cin =  "10e-12" *)
  output wire cout;

  // Full adder combinational logic
  assign sum = a ^ b ^ cin;
  assign cout = ((a ^ b) & cin) | (a & b);

  // Timing parameters, not supported by Yosys at the moment.
`ifndef YOSYS
  `timescale 1ps/1ps
  specify
    specparam T1 300;
    specparam T2 10;
    // (input->output) min:typ:max

    (a => sum)  = T1;
    (b => sum)  = T1;
    (cin => sum)  = T1;

    (a => cout) = T1;
    (b => cout) = T1;
    (cin => cout) = T2;

  endspecify
`endif
endmodule
adder.model.xml
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<?xml version="1.0"?>
<models>
  <model name="ADDER">
    <input_ports>
      <port combinational_sink_ports="cout sum" name="a"/>
      <port combinational_sink_ports="cout sum" name="b"/>
      <port combinational_sink_ports="cout sum" name="cin"/>
    </input_ports>
    <output_ports>
      <port name="cout"/>
      <port name="sum"/>
    </output_ports>
  </model>
</models>
adder.pb_type.xml
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<?xml version="1.0"?>
<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" blif_model=".subckt ADDER" name="ADDER" num_pb="1">
  <input name="a" num_pins="1"/>
  <input name="b" num_pins="1"/>
  <input name="cin" num_pins="1"/>
  <output name="cout" num_pins="1"/>
  <output name="sum" num_pins="1"/>
  <delay_constant in_port="ADDER.a" max="300e-12" out_port="ADDER.cout"/>
  <delay_constant in_port="ADDER.b" max="300e-12" out_port="ADDER.cout"/>
  <delay_constant in_port="ADDER.cin" max="10e-12" out_port="ADDER.cout"/>
  <delay_constant in_port="ADDER.a" max="300e-12" out_port="ADDER.sum"/>
  <delay_constant in_port="ADDER.b" max="300e-12" out_port="ADDER.sum"/>
  <delay_constant in_port="ADDER.cin" max="300e-12" out_port="ADDER.sum"/>
</pb_type>

Detection of combinational connections

  • Output has combinational connection with input

Blackbox detection

  • Model of the leaf pb_type is generated

  • Leaf pb_type XML is generated

Timings

  • All the timings defined for wires with attributes should be included in pb_type XML