Set outputs as clock by name (multiple clock outputs)¶
output wire rdclk
and output wire wrclk
have clk
in their names, hence are recognized as clock inputs by v2x.
19 20 21 22 23 24 25 26 27 28 29 30 | /*
* `output wire rdclk` and `output wire wrclk` should be detected as a clock
* despite this being a black box module.
*/
(* whitebox *)
module BLOCK(a, b, rdclk, o, wrclk);
input wire a;
input wire b;
output wire rdclk;
output wire o;
output wire wrclk;
endmodule
|
As such, the is_clock
attribute of the rdclk
and wrclk
ports are set to 1.
<?xml version="1.0"?>
<models>
<model name="BLOCK">
<input_ports>
<port name="a"/>
<port name="b"/>
</input_ports>
<output_ports>
<port name="o"/>
<port is_clock="1" name="rdclk"/>
<port is_clock="1" name="wrclk"/>
</output_ports>
</model>
</models>