Set output as clock by name (clk)

An output wire can be set as a clock by assigning clk as its name.

tests/clocks/output_named_clk/output_named_clk.sim.v

/*
 * `output wire clk` should be detected as a clock despite this being a black
 * box module.
 */
(* whitebox *)
module BLOCK(a, b, clk);
  input wire a;
  input wire b;
  output wire clk;
endmodule

As such, the is_clock attribute of the clk output port is set to 1.

output_named_clk.model.xml

<?xml version="1.0"?>
<models>
  <model name="BLOCK">
    <input_ports>
      <port name="a"/>
      <port name="b"/>
    </input_ports>
    <output_ports>
      <port is_clock="1" name="clk"/>
    </output_ports>
  </model>
</models>