D-Flipflop with combinational logic¶
The following shows a combinational logic design driven by a clock. input wire a
should be detected as a clock because it drives the flip flop.
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 | /*
* `input wire a` should be detected as a clock because it drives the flip
* flop.
*/
module BLOCK(a, b, c, d);
input wire a;
input wire b;
input wire c;
output wire d;
reg r;
always @ ( posedge a ) begin
r <= b | ~c;
end
assign d = r;
endmodule
|
The is_clock
attribute of the a
port is set to 1, and the ports b
, c
and d
have their clock
attribute set to a
.
<?xml version="1.0"?>
<models>
<model name="BLOCK">
<input_ports>
<port is_clock="1" name="a"/>
<port clock="a" combinational_sink_ports="d" name="b"/>
<port clock="a" combinational_sink_ports="d" name="c"/>
</input_ports>
<output_ports>
<port clock="a" name="d"/>
</output_ports>
</model>
</models>