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F4PGA Verilog to XML (V2X) 0.0-618-g413dc27 documentation Manually set outputs as clock

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F4PGA Verilog to XML (V2X) 0.0-618-g413dc27 documentation
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F4PGA Verilog to XML (V2X) 0.0-618-g413dc27 documentation

chipsalliance/f4pga-v2x

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Manually set outputs as clock¶

Manually set output as clock by setting the CLOCK attribute
Set output as clock by name (clk)

Previous Set input as clock by name (regex)

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