Set input as clock by name (clk)

An input wire can be set as a clock by assigning clk as its name.

tests/clocks/input_named_clk/input_named_clk.sim.v

/*
 * `input wire clk` should be detected as a clock despite this being a black
 * box module.
 */
(* whitebox *)
module BLOCK(clk, a, o);
  input wire clk;
  input wire a;
  output wire o;
endmodule

As such, the is_clock attribute of the clk port is set to 1, without needing to set anything else in the verilog code.

input_named_clk.model.xml

<?xml version="1.0"?>
<models>
  <model name="BLOCK">
    <input_ports>
      <port name="a"/>
      <port is_clock="1" name="clk"/>
    </input_ports>
    <output_ports>
      <port name="o"/>
    </output_ports>
  </model>
</models>