D-Flipflop with two clocks

input wire c1 and input wire c2 should be detected as clocks because they drive the flip flop.

tests/clocks/dff_two_clocks/dff_two_clocks.sim.v

module BLOCK(c1, c2, a, b, c, o1, o2);
  input wire c1;
  input wire c2;
  input wire a;
  input wire b;
  input wire c;
  output wire o1;
  output wire o2;

  reg r1;
  reg r2;
        always @ ( posedge c1 ) begin
                r1 <= a | b;
        end
        always @ ( posedge c2 ) begin
                r2 <= b | c;
        end

  assign o1 = r1;
  assign o2 = r2;
endmodule

The is_clock attribute of the c1 and c2 ports are set to 1, and the ports a, b, c, o1 and o2 have their clock attribute set to the respective clocks they are driven by.

dff_two_clocks.model.xml

<?xml version="1.0"?>
<models>
  <model name="BLOCK">
    <input_ports>
      <port clock="c1" combinational_sink_ports="o1" name="a"/>
      <port clock="c2 c1" combinational_sink_ports="o2 o1" name="b"/>
      <port clock="c2" combinational_sink_ports="o2" name="c"/>
      <port is_clock="1" name="c1"/>
      <port is_clock="1" name="c2"/>
    </input_ports>
    <output_ports>
      <port clock="c1" name="o1"/>
      <port clock="c2" name="o2"/>
    </output_ports>
  </model>
</models>