Pack pattern annotation

This example shows that v2x prevents annotating a top-level port of a pb_type when a net of that port is forking. This enables using pack patterns, e.g., for LUT to FF connections when the LUT output is also connected to a top-level output port.

/home/docs/checkouts/readthedocs.org/user_builds/f4pga-v2x/checkouts/latest/docs/examples/pack_pattern/pack_pattern.sim.v
pack_pattern.sim.v
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`include "./lut4/lut4.sim.v"
`include "./dff/dff.sim.v"

module PACK_PATTERN (
    CLK,
    LUT_IN,
    LUT_OUT,
    DFF_OUT
);
    input wire CLK;
    input wire [3:0] LUT_IN;

    output wire LUT_OUT;
    output wire DFF_OUT;

    (* pack *)
    wire w;

    LUT4 lut (.I(LUT_IN), .O(w));
    DFF dff (.CLK(CLK), .D(w), .Q(DFF_OUT));

    assign LUT_OUT = w;
endmodule
pack_pattern.model.xml
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<?xml version="1.0"?>
<models>
  <model name="DFF">
    <input_ports>
      <port is_clock="1" name="CLK"/>
      <port clock="CLK" name="D"/>
    </input_ports>
    <output_ports>
      <port clock="CLK" name="Q"/>
    </output_ports>
  </model>
  <model name="LUT4">
    <input_ports>
      <port combinational_sink_ports="O" name="I"/>
    </input_ports>
    <output_ports>
      <port name="O"/>
    </output_ports>
  </model>
</models>
pack_pattern.pb_type.xml
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<?xml version="1.0"?>
<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" name="PACK_PATTERN" num_pb="1">
  <clock name="CLK" num_pins="1"/>
  <input name="LUT_IN" num_pins="4"/>
  <output name="DFF_OUT" num_pins="1"/>
  <output name="LUT_OUT" num_pins="1"/>
  <pb_type blif_model=".subckt DFF" name="dff" num_pb="1">
    <clock name="CLK" num_pins="1"/>
    <input name="D" num_pins="1"/>
    <output name="Q" num_pins="1"/>
    <T_setup clock="CLK" port="DFF.D" value="10e-12"/>
    <T_hold clock="CLK" port="DFF.D" value="10e-12"/>
    <T_clock_to_Q clock="CLK" max="10e-12" port="DFF.Q"/>
  </pb_type>
  <pb_type blif_model=".subckt LUT4" name="lut" num_pb="1">
    <input name="I" num_pins="4"/>
    <output name="O" num_pins="1"/>
    <delay_matrix in_port="LUT4.I" out_port="LUT4.O" type="max">
30e-12 20e-12 11e-12 3e-12
</delay_matrix>
  </pb_type>
  <interconnect>
    <direct input="dff.Q" name="PACK_PATTERN-DFF_OUT" output="PACK_PATTERN.DFF_OUT"/>
    <direct input="lut.O" name="PACK_PATTERN-LUT_OUT" output="PACK_PATTERN.LUT_OUT"/>
    <direct input="PACK_PATTERN.CLK" name="dff-CLK" output="dff.CLK"/>
    <direct input="lut.O" name="dff-D" output="dff.D">
      <pack_pattern in_port="lut.O" name="pack-00000000000000000000000000000001" out_port="dff.D"/>
    </direct>
    <direct input="PACK_PATTERN.LUT_IN[0]" name="lut-I[0]" output="lut.I[0]"/>
    <direct input="PACK_PATTERN.LUT_IN[1]" name="lut-I[1]" output="lut.I[1]"/>
    <direct input="PACK_PATTERN.LUT_IN[2]" name="lut-I[2]" output="lut.I[2]"/>
    <direct input="PACK_PATTERN.LUT_IN[3]" name="lut-I[3]" output="lut.I[3]"/>
  </interconnect>
</pb_type>