Classical D-Flip-Flop test¶
An example of the classical D-Flip-Flop shown in Figure 60 - DFF
.
Fig. 60 - DFF
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 | `ifndef DFF
`define DFF
(* whitebox *)
module DFF (D, CLK, Q);
input wire CLK;
(* SETUP="CLK 10e-12" *)
(* HOLD="CLK 10e-12" *)
input wire D;
(* CLK_TO_Q="CLK 10e-12" *)
output reg Q;
always @ ( posedge CLK ) begin
Q <= D;
end
`ifndef YOSYS
specify
specparam
tplh$CLK$QP = 1.0,
tphl$CLK$QP = 1.0,
tplh$CLK$QN = 1.0,
tphl$CLK$QN = 1.0,
tsetup$D$CLK = 1.0,
thold$D$CLK = 1.0,
tminpwl$CLK = 1.0,
tminpwh$CLK = 1.0;
// PATH DELAYS
if (flag)
// Polarity of QP is positive referenced to D
(posedge CLK *> (QP +: D)) = (tplh$CLK$QP, tphl$CLK$QP);
if (flag)
// Polarity of QN is negative referenced to D
(posedge CLK *> (QN -: D)) = (tplh$CLK$QN, tphl$CLK$QN);
// SETUP AND HOLD CHECKS
$setuphold(posedge CLK &&& (flag == 1), posedge D, tsetup$D$CLK, thold$D$CLK, NOTIFIER);
$setuphold(posedge CLK &&& (flag == 1), negedge D, tsetup$D$CLK, thold$D$CLK, NOTIFIER);
// MINIMUM WIDTH CHECKING
$width(negedge CLK, tminpwl$CLK, 0, NOTIFIER);
$width(posedge CLK, tminpwh$CLK, 0, NOTIFIER);
endspecify
`endif
endmodule
`endif
|
1 2 3 4 5 6 7 8 9 10 11 12 | <?xml version="1.0"?>
<models>
<model name="DFF">
<input_ports>
<port is_clock="1" name="CLK"/>
<port clock="CLK" name="D"/>
</input_ports>
<output_ports>
<port clock="CLK" name="Q"/>
</output_ports>
</model>
</models>
|
1 2 3 4 5 6 7 8 9 | <?xml version="1.0"?>
<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" blif_model=".subckt DFF" name="DFF" num_pb="1">
<clock name="CLK" num_pins="1"/>
<input name="D" num_pins="1"/>
<output name="Q" num_pins="1"/>
<T_setup clock="CLK" port="DFF.D" value="10e-12"/>
<T_hold clock="CLK" port="DFF.D" value="10e-12"/>
<T_clock_to_Q clock="CLK" max="10e-12" port="DFF.Q"/>
</pb_type>
|
Clock associations inference¶
Automatic inference is signal is associated with any clock and include the info in the model
Automatic clock detection (signals named
clk
are considered as clocks)
Blackbox detection¶
Model of the leaf
pb_type
is generatedLeaf
pb_type
XML is generated
Timings¶
All the timings defined for wires with attributes should be included in
pb_type
XML