DSP-style block with all inputs registered

A combinational DSP block with registered inputs. Modeled as a complex block.

tests/dsp/dsp_in_registered/dsp_in_registered.sim.v

`include "./dff/dff.sim.v"
`include "./dsp_combinational/dsp_combinational.sim.v"

/* DSP Block with register on all inputs */
module DSP_IN_REGISTERED (clk, a, b, m, out);
  localparam DATA_WIDTH = 4;

  input wire clk;
  input wire [DATA_WIDTH/2-1:0] a;
  input wire [DATA_WIDTH/2-1:0] b;
  input wire m;
  output wire [DATA_WIDTH-1:0] out;

  /* Input registers */
  (* pack="DFF2DSP" *)
  wire [DATA_WIDTH/2-1:0] q_a;
  (* pack="DFF2DSP" *)
  wire [DATA_WIDTH/2-1:0] q_b;
  (* pack="DFF2DSP" *)
  wire q_m;

  genvar i;
  for (i=0; i<DATA_WIDTH/2; i=i+1) begin
    DFF q_a_ff(.D(a[i]), .Q(q_a[i]), .CLK(clk));
    DFF q_b_ff(.D(b[i]), .Q(q_b[i]), .CLK(clk));
  end
  DFF m_ff(.D(m), .Q(q_m), .CLK(clk));

  /* Combinational Logic */
  DSP_COMBINATIONAL comb (.a(q_a), .b(q_b), .m(q_m), .out(out));
endmodule

dsp_in_registered.model.xml

<?xml version="1.0"?>
<models>
  <model name="DFF">
    <input_ports>
      <port is_clock="1" name="CLK"/>
      <port clock="CLK" name="D"/>
    </input_ports>
    <output_ports>
      <port clock="CLK" name="Q"/>
    </output_ports>
  </model>
  <model name="DSP_COMBINATIONAL">
    <input_ports>
      <port combinational_sink_ports="out" name="a"/>
      <port combinational_sink_ports="out" name="b"/>
      <port combinational_sink_ports="out" name="m"/>
    </input_ports>
    <output_ports>
      <port name="out"/>
    </output_ports>
  </model>
</models>

dsp_in_registered.pb_type.xml

<?xml version="1.0"?>
<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" name="DSP_IN_REGISTERED" num_pb="1">
  <clock name="clk" num_pins="1"/>
  <input name="a" num_pins="2"/>
  <input name="b" num_pins="2"/>
  <input name="m" num_pins="1"/>
  <output name="out" num_pins="4"/>
  <pb_type blif_model=".subckt DSP_COMBINATIONAL" name="comb" num_pb="1">
    <input name="a" num_pins="2"/>
    <input name="b" num_pins="2"/>
    <input name="m" num_pins="1"/>
    <output name="out" num_pins="4"/>
    <delay_constant in_port="DSP_COMBINATIONAL.a" max="30e-12" out_port="DSP_COMBINATIONAL.out"/>
    <delay_constant in_port="DSP_COMBINATIONAL.b" max="30e-12" out_port="DSP_COMBINATIONAL.out"/>
    <delay_constant in_port="DSP_COMBINATIONAL.m" max="10e-12" out_port="DSP_COMBINATIONAL.out"/>
  </pb_type>
  <pb_type blif_model=".subckt DFF" name="m_ff" num_pb="1">
    <clock name="CLK" num_pins="1"/>
    <input name="D" num_pins="1"/>
    <output name="Q" num_pins="1"/>
    <T_setup clock="CLK" port="DFF.D" value="10e-12"/>
    <T_hold clock="CLK" port="DFF.D" value="10e-12"/>
    <T_clock_to_Q clock="CLK" max="10e-12" port="DFF.Q"/>
  </pb_type>
  <pb_type blif_model=".subckt DFF" name="q_a_ff" num_pb="2">
    <clock name="CLK" num_pins="1"/>
    <input name="D" num_pins="1"/>
    <output name="Q" num_pins="1"/>
    <T_setup clock="CLK" port="DFF.D" value="10e-12"/>
    <T_hold clock="CLK" port="DFF.D" value="10e-12"/>
    <T_clock_to_Q clock="CLK" max="10e-12" port="DFF.Q"/>
  </pb_type>
  <pb_type blif_model=".subckt DFF" name="q_b_ff" num_pb="2">
    <clock name="CLK" num_pins="1"/>
    <input name="D" num_pins="1"/>
    <output name="Q" num_pins="1"/>
    <T_setup clock="CLK" port="DFF.D" value="10e-12"/>
    <T_hold clock="CLK" port="DFF.D" value="10e-12"/>
    <T_clock_to_Q clock="CLK" max="10e-12" port="DFF.Q"/>
  </pb_type>
  <interconnect>
    <direct input="comb.out[0]" name="DSP_IN_REGISTERED-out[0]" output="DSP_IN_REGISTERED.out[0]"/>
    <direct input="comb.out[1]" name="DSP_IN_REGISTERED-out[1]" output="DSP_IN_REGISTERED.out[1]"/>
    <direct input="comb.out[2]" name="DSP_IN_REGISTERED-out[2]" output="DSP_IN_REGISTERED.out[2]"/>
    <direct input="comb.out[3]" name="DSP_IN_REGISTERED-out[3]" output="DSP_IN_REGISTERED.out[3]"/>
    <direct input="q_a_ff[0].Q" name="comb-a[0]" output="comb.a[0]">
      <pack_pattern in_port="q_a_ff[0].Q" name="pack-DFF2DSP" out_port="comb.a[0]"/>
    </direct>
    <direct input="q_a_ff[1].Q" name="comb-a[1]" output="comb.a[1]">
      <pack_pattern in_port="q_a_ff[1].Q" name="pack-DFF2DSP" out_port="comb.a[1]"/>
    </direct>
    <direct input="q_b_ff[0].Q" name="comb-b[0]" output="comb.b[0]">
      <pack_pattern in_port="q_b_ff[0].Q" name="pack-DFF2DSP" out_port="comb.b[0]"/>
    </direct>
    <direct input="q_b_ff[1].Q" name="comb-b[1]" output="comb.b[1]">
      <pack_pattern in_port="q_b_ff[1].Q" name="pack-DFF2DSP" out_port="comb.b[1]"/>
    </direct>
    <direct input="m_ff.Q" name="comb-m" output="comb.m">
      <pack_pattern in_port="m_ff.Q" name="pack-DFF2DSP" out_port="comb.m"/>
    </direct>
    <direct input="DSP_IN_REGISTERED.clk" name="m_ff-CLK" output="m_ff.CLK"/>
    <direct input="DSP_IN_REGISTERED.m" name="m_ff-D" output="m_ff.D"/>
    <direct input="DSP_IN_REGISTERED.clk" name="q_a_ff[0]-CLK" output="q_a_ff[0].CLK"/>
    <direct input="DSP_IN_REGISTERED.a[0]" name="q_a_ff[0]-D" output="q_a_ff[0].D"/>
    <direct input="DSP_IN_REGISTERED.clk" name="q_a_ff[1]-CLK" output="q_a_ff[1].CLK"/>
    <direct input="DSP_IN_REGISTERED.a[1]" name="q_a_ff[1]-D" output="q_a_ff[1].D"/>
    <direct input="DSP_IN_REGISTERED.clk" name="q_b_ff[0]-CLK" output="q_b_ff[0].CLK"/>
    <direct input="DSP_IN_REGISTERED.b[0]" name="q_b_ff[0]-D" output="q_b_ff[0].D"/>
    <direct input="DSP_IN_REGISTERED.clk" name="q_b_ff[1]-CLK" output="q_b_ff[1].CLK"/>
    <direct input="DSP_IN_REGISTERED.b[1]" name="q_b_ff[1]-D" output="q_b_ff[1].D"/>
  </interconnect>
</pb_type>

Detection of combinational connections

• Output has combinational connection with input

• pack_pattern defined on wire connections with pack attribute

Blackbox detection

• Model of the leaf pb_type is generated

• Leaf pb_type XML is generated

• All dependency models and pb_types are included in the output files