Manually set input as clock by setting the CLOCK attribute¶
The following shows that input wire a
is given the (* CLOCK *)
attribute.
19 20 21 22 23 24 25 26 27 28 29 | /*
* `input wire a` should be detected as a clock because of the `(* CLOCK *)`
* attribute.
*/
(* whitebox *)
module BLOCK(a, b, o);
(* CLOCK *)
input wire a;
input wire b;
output wire o;
endmodule
|
As such, the is_clock
attribute of the a
port is set to 1.
<?xml version="1.0"?>
<models>
<model name="BLOCK">
<input_ports>
<port is_clock="1" name="a"/>
<port name="b"/>
</input_ports>
<output_ports>
<port name="o"/>
</output_ports>
</model>
</models>