Combinational DSP¶
A combinational DSP block capable of multiplication and division. Modeled as “combinational block” according to Figure 60
of Primitive Block Timing Modeling Tutorial.
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 | `ifndef DSP_COMB
`define DSP_COMB
(* whitebox *)
module DSP_COMBINATIONAL (
a, b, m,
out
);
localparam DATA_WIDTH = 4;
input wire [DATA_WIDTH/2-1:0] a;
input wire [DATA_WIDTH/2-1:0] b;
input wire m;
(* DELAY_CONST_a="30e-12" *)
(* DELAY_CONST_b="30e-12" *)
(* DELAY_CONST_m="10e-12" *)
output wire [DATA_WIDTH-1:0] out;
// Full adder combinational logic
assign out = m ? a * b : a / b;
endmodule
`endif
|
1 2 3 4 5 6 7 8 9 10 11 12 13 | <?xml version="1.0"?>
<models>
<model name="DSP_COMBINATIONAL">
<input_ports>
<port combinational_sink_ports="out" name="a"/>
<port combinational_sink_ports="out" name="b"/>
<port combinational_sink_ports="out" name="m"/>
</input_ports>
<output_ports>
<port name="out"/>
</output_ports>
</model>
</models>
|
1 2 3 4 5 6 7 8 9 10 | <?xml version="1.0"?>
<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" blif_model=".subckt DSP_COMBINATIONAL" name="DSP_COMBINATIONAL" num_pb="1">
<input name="a" num_pins="2"/>
<input name="b" num_pins="2"/>
<input name="m" num_pins="1"/>
<output name="out" num_pins="4"/>
<delay_constant in_port="DSP_COMBINATIONAL.a" max="30e-12" out_port="DSP_COMBINATIONAL.out"/>
<delay_constant in_port="DSP_COMBINATIONAL.b" max="30e-12" out_port="DSP_COMBINATIONAL.out"/>
<delay_constant in_port="DSP_COMBINATIONAL.m" max="10e-12" out_port="DSP_COMBINATIONAL.out"/>
</pb_type>
|
Detection of combinational connections¶
Output has combinational connection with input
Blackbox detection¶
Model of the leaf
pb_type
is generatedLeaf
pb_type
XML is generated