Primitive Block Timing Modeling Tutorial

The following shows examples taken from the Primitive Block Timing Modeling Tutorial in the Verilog to Routing documentation.

• Classical D-Flip-Flop test
  • Clock associations inference
  • Blackbox detection
  • Timings
• Full Adder Example
  • Detection of combinational connections
  • Blackbox detection
  • Timings
• LUT with FlipFlop Example
  • Blackbox detection
  • Carry chain inference