D-Flipflop with one clock

The following shows a simple D-flip flop driven by one clock. input wire a should be detected as a clock because it drives the flip flop.

tests/clocks/dff_one_clock/dff_one_clock.sim.v

/*
 * `input wire a` should be detected as a clock because it drives the flip
 * flop.
 */
module BLOCK(a, b, c);
  input wire a;
  input wire b;
  output wire c;

  reg r;
  always @ ( posedge a ) begin
    r <= b;
  end
  assign c = r;
endmodule

As you can see in the generated model, the is_clock attribute of the a port is set to 1, while the b and c ports have their clock attribute set to a.

dff_one_clock.model.xml

<?xml version="1.0"?>
<models>
  <model name="BLOCK">
    <input_ports>
      <port is_clock="1" name="a"/>
      <port clock="a" name="b"/>
    </input_ports>
    <output_ports>
      <port clock="a" name="c"/>
    </output_ports>
  </model>
</models>